1. Field of the Invention
The present invention relates to a timing simulation system for verifying the circuit operating characteristics and the electrical delay characteristics of a layout pattern of a logic circuit.
2. Description of the Related Art
FIG. 6 is a block diagram of a conventional timing simulation system. A layout pattern data storage portion 1 for storing layout pattern data equivalent to a logic circuit is connected to a data extracting portion 2 for extracting circuit constant data and wiring area data from the layout pattern data. The data extracting portion 2 is connected to a circuit constant data storage portion 3 and a wiring area data storage portion 4 for storing the extracted circuit constant data and wiring area data, respectively. The circuit constant data storage portion 3 and the wiring area data storage portion 4 are connected to a delay value calculating portion 7 for calculating a delay to be set in each of gate elements constituting a logic circuit. Furthermore, the delay value calculating portion 7 is connected to a process parameter storage portion 5 for storing various process parameters which are necessary for the production of the logic circuit, and an operating condition data storage portion 6 for storing operation condition data, such as a supply voltage v, an ambient temperature t and a dispersion variable p of processes carried out in production.
On the other hand, a circuit diagram input portion 8 for inputting circuit diagram data equivalent to the logic circuit and a circuit connection data supply portion 9 for creating circuit connection data are connected to each other. The circuit connection data supply portion 9 is connected to a circuit connection data storage portion 11. The delay value calculating portion 7 is connected to a delay value supply portion 10 for setting the calculated delay in an applicable gate element in the circuit connection data, and the delay value supply portion 10 is connected to the circuit connection data storage portion 11. Furthermore, the circuit connection data storage portion 11 is connected to a logic simulation executing portion 13 for conducting logic simulation on a circuit model where each element has a delay value peculiar thereto. The logic simulation executing portion 13 is connected to an input pattern data storage portion 12 for storing test pattern data to be input to the circuit connection data, and a simulation result output portion 14 for displaying the simulation result, such as signal value change information.
Operation of the conventional timing simulation system will now be described with reference to FIGS. 7 and 8. FIG. 7 is a circuit diagram of a logic circuit as a component of a large-scale digital circuit to be simulated. Referring to FIG. 7, the logic circuit is composed of PMOS transistors G1, G4 and G6, NMOS transistors G2, G3, G5 and G7, input signal lines N1, N2 and N3 of the transistors G1, G2 and G3, respectively, an internal signal line N4 connected to a contact of the transistors G1 and G2, and an internal signal line N5 connected to a contact of the transistors G2 and G3.
FIG. 8 shows layout pattern data corresponding to a part of the logic circuit shown in FIG. 7. The layout pattern data shown in FIG. 8 includes diffusion regions 15 and 16, polysilicon regions 17 and 18, an aluminum (A1) wiring region 19, contact regions 20 and 21, and gate forming regions 22 and 23 of transistors Q1 and Q2 where the diffusion regions 15 and 16 are overlaid on the polysilicon regions 17 and 18, respectively. The transistors Q1 and Q2 each correspond to any pair of the transistors G1 to G7 shown in FIG. 7.
If the circuit designer inputs the circuit diagram data shown in FIG. 8 from the circuit diagram input portion 8 shown in FIG. 6, the circuit connection data supply portion 9 obtains circuit connection data from the input circuit diagram data, and stores the circuit connection data in the circuit connection data storage portion 11. Subsequently, layout pattern data is created and stored in the layout pattern data storage portion 1. Circuit constant data and wiring area data are extracted from the layout pattern data by the data extracting portion 2, and stored in the circuit constant data storage portion 3 and the wiring area data storage portion 4, respectively. As the circuit constant data, for example, the channel length L.sub.1 and the channel width W.sub.1 of the transistor Q1 shown in FIG. 8 are extracted, and as the wiring area data, for example, the width a.sub.1 and the length b.sub.1 of the drain diffusion region 15a of the transistor Q1, the area A.sub.M of the aluminum wiring region 19, the area A.sub.p of the polysilicon region 18, and the area A.sub.G2 of the gate of the transistor Q2, are extracted.
Then, the delay value calculating portion 7 reads the circuit constant data and the wiring area data out of the circuit constant data storage portion 3 and the wiring area data storage portion 4, reads process parameters and operating condition data stored in the process parameter storage portion 5 and the operating condition data storage portion 6, and substitutes the above data in a general delay calculating expression, thereby calculating a delay d. The delay value supply portion 10 sets the calculated delay d as the delay of the transistor Q1 in the circuit connection data.
By executing the above-mentioned processes, that is, the extraction of the circuit constant data and the wiring area data and the calculation and supply of the delay, circuit connection data including a delay is created as shown in the following Table 1.
TABLE 1 __________________________________________________________________________ GATE=G1, ETYPE=P, G=N1, SD=VDD, SD=N4, DELAY=d1; GATE=G2, ETYPE=N, G=N2, SD=N4, SD=N5, DELAY=d2; GATE=G3, ETYPE=N, G=N3, SD=N5, SD=GND, DELAY=d3; .vertline. .vertline. .vertline. .vertline. .vertline. .vertline. 31 32 33 34 35 36 __________________________________________________________________________
In Table 1, numerals 31 and 32 denote a gate name peculiar to an element, and a type of the element, respectively. P and N designate a PMOS transistor and an NMOS transistor, respectively. Numerals 33, 34 and 35 denote signal lines (nets) connected to a gate terminal, a source terminal and a drain terminal of the element. Numeral 36 denotes a delay for the element.
Subsequently, the logic simulation executing portion 13 executes a logic simulation based on the circuit connection data with the delays shown in the above Table 1 and test pattern data for function evaluation stored in the input pattern data storage portion 12, and the simulation result output portion 14 displays the result of the simulation, such as signal change information, to the circuit designer.
If a transistor element as a component of an actual circuit operates at the switch level, that is, functions as a pass gate, since a group of nets which become equivalent in potential in response to ON/OFF switching of the transistor dynamically change, the total load capacity of the nets also changes dynamically. As a result, the total gain coefficient of transistors for driving such nets, and the signal value propagation delay value among the transistor elements also dynamically change.
However, in the case of the above-mentioned prior art which verifies the dynamic characteristics of a large scale digital circuit at high speed, a delay corresponding to layout pattern information is first calculated, and set as a constant peculiar to elements constituting the circuit, and then operation of the circuit is simulated. Therefore, it is difficult to simulate a precise delay.
For example, if a logical signal value changes from 0 to 1 on the input signal line N3 in the circuit shown in FIG. 7 and thus an output signal value of the transistor G3, that is, a signal on the net N5 changes, a signal value propagation delay time d.sub.t with respect to the transistors G6 and G7 in the next stage varies in accordance with whether the transistor G2 connected to the net N5 is ON. However, since the delay time is set as a constant peculiar to the transistor G3 in the conventional timing simulation system, actual operation of the circuit cannot be simulated precisely.